vishay siliconix sip32452, sip32453 document number: 63315 s11-1695-rev. b, 22-aug-11 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 1 v, 55 m ? load switch in micro foot ? description sip32452 and sip32453 are n-channel integrated high side load switches that operate fr om 0.9 v to 2.5 v input voltage range. sip32452 and sip32453 has low input logic control threshold that can interface with low voltage control gpio directly without extra level shift or driver. there is a pull down at this en logic control pin. turn on time is fast in less than 25 s typically for input voltage of 1.2 v or higher. sip32452 has fast turn off delay time of less than 1 s while sip32453 features a guaranteed turn off delay of greater than 30 s, typically 90 s. both sip32452 and sip32453 are available in compact wafer level csp package, micro foot ? 4 bumps 0.8 mm x 0.8 mm with 0.4 mm pitch. features ? halogen-free accord ing to iec 61249-2-21 definition ? low input voltage, 0.9 v to 2.5 v ?low r on , 55 m ? typical ? fast turn on time ? low logic control with hysteresis ? reverse current blocking when disabled ? integrated pull down at en pin ? 4-bump micro foot ? package ? compliant to rohs directive 2002/95/ec applications ? battery operated devices ? smart phones ? gps and pmp ? computer ? medical and healthcare equipment ? industrial and instrument ? cellular phones and portable media players ? game console typical application circuit figure 1 - sip32452 and sip32453 typical application circuit sip32452, sip32453 i n v out out v i n g n d g n d g n d e n e n c 4.7 f i n c 0.1 f out
www.vishay.com 2 document number: 63315 s11-1695-rev. b, 22-aug-11 vishay siliconix sip32452, sip32453 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 note: ge1 denotes halogen-free and rohs compliant notes: a. device mounted with all leads and power pad soldered or welded to pc board. b. derate 3.6 mw/c above t a = 70 c. stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating/conditions for extended periods may affect device reliability. ordering information temperature range package marking part number - 40 c to 85 c micro foot ? : 4 bumps (2 x 2, 0.4 mm pitch, 208 m bump height) ab SIP32452DB-T2-GE1 ac sip32453db-t2-ge1 absolute maximum ratings parameter limit unit supply input voltage (v in ) - 0.3 to 2.75 v enable input voltage (v en ) - 0.3 to 2.75 output voltage (v out ) - 0.3 to 2.75 maximum continuous switch current (i max. )1.2 a maximum pulsed current (i dm ) v in (pulsed at 1 ms, 10 % duty cycle) 2 esd rating (hbm) 4000 v junction temperature (t j ) - 40 to 125 c thermal resistance ( ? ja ) a 280 c/w power dissipation (p d ) a 196 mw recommended operating range parameter limit unit input voltage range (v in ) 0.9 to 2.5 v operating temperature range - 40 to 85 c
document number: 63315 s11-1695-rev. b, 22-aug-11 www.vishay.com 3 vishay siliconix sip32452, sip32453 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. the algebraic convention whereby the most negative value is a minimu m and the most positive a maximum. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. for v in outside this range consult ty pical en threshold curve. specifications parameter symbol test conditions unless specified v in = 1 v, t a = - 40 c to 85 c (typical values are at t a = 25 c) limits unit min. a typ. b max. a operating voltage c v in 0.9 - 2.5 v quiescent current i q v in = 1.2 v, v en = v in , out = open -1015 a v in = 2.5 v, v en = v in , out = open -3460 off supply current i q(off) en = gnd, out = open - - 1 off switch current i ds(off) en = gnd, out = 0 v - - 30 reverse blocking current i rb v out = 2.5 v, v in = 0.9 v, v en = 0 v - 0.001 10 on-resistance r ds(on) v in = 1 v, i l = 200 ma, t a = 25 c -5665 m ? v in = 1.2 v, i l = 200 ma, t a = 25 c -5565 v in = 1.8 v, i l = 200 ma, t a = 25 c -5465 v in = 2.5 v, i l = 200 ma, t a = 25 c -5465 on-resistance temp.-coefficient tc rds - 3900 - ppm/c en input low voltage c v il v in = 1 v --0.1 v en input high voltage c v ih v in = 2.5 v 1.5 - - en input leakage i en v in = 2.5 v, v en = 0 v --1 a v in = 2.5 v, v en = 2.5 v -1015 output turn-on delay time t d(on) both, v in = 1.2 v r load = 10 ? , c l = 0.1 f t a = 25 c -0.41 s both, v in = 2.5 v -0.051 output turn-on rise time t r both, v in = 1.2 v 10 20 30 both, v in = 2.5 v 59.820 output turn-off delay time t d(off) sip32452, v in = 1.2 v -0.251 sip32452, v in = 2.5 v -0.151 sip32453, v in = 1.2 v 30 98 150 sip32453, v in = 2.5 v 30 86 150
www.vishay.com 4 document number: 63315 s11-1695-rev. b, 22-aug-11 vishay siliconix sip32452, sip32453 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pin configuration typical characteristics (internally regulated, 25 c, unless otherwise noted) figure 2 - micro foot ? 2 x 2 package a b en gnd out in index-bump a1 w b a 12 out in 1 2 a b en gnd backside bumpside pin description pin number name function a1 in this pin is the n-channel mosfet drain connec tion. bypass to ground through a 4.7 f capacitor. a2 out this pin is the n-channel mosfet source co nnection. bypass to ground th rough a 0.1 f capacitor. b1 en enable input b2 gnd ground connection figure 3 - quiescent current vs. input voltage figure 5 - off supply current vs. input voltage 0 5 10 15 20 25 30 35 40 45 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 i q - quiescent current (a) v in (v) v in (v) i q(off) - off supply current (na) 0 2 4 6 8 10 12 0.8 1.2 1.6 2.0 2.4 2.8 figure 4 - quiescent current vs. temperature figure 6 - off supply current vs. temperature 100 0 5 10 15 20 25 30 35 40 45 50 - 40 - 20 0 20 40 60 80 i q - quiescent current (a) temperature (c) v in = 1 v v in = 2.5 v v in = 1.2 v temperature (c) i q(off) - off supply current (na) 0.0001 0.001 0.01 0.1 1 10 100 1000 - 40 - 20 0 20 40 60 80 100 v in = 2.5 v v in = 1.2 v v in = 1 v
document number: 63315 s11-1695-rev. b, 22-aug-11 www.vishay.com 5 vishay siliconix sip32452, sip32453 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (internally regulated, 25 c, unless otherwise noted) figure 7 - off switch current vs. input voltage figure 9 - r ds(on) vs. v in figure 11 - i en vs. v en v in (v) i ds(off) - off switch current (na) 200 300 400 500 600 700 800 900 1000 0.8 1.2 1.6 2 2.4 2.8 v in (v) r ds - on-resistance (m ) 50 52 54 56 58 60 62 64 66 0.8 1.2 1.6 2.0 2.4 2.8 i o = 0.2 a i o = 0.5 a i o = 1.2 a v en (v) i en - en current (a) 0 2 4 6 8 10 12 0 0.5 1 1.5 2 2.5 v in = 2.5 v figure 8 - off switch current vs. temperature figure 10 - r ds(on) vs. temperature figure 12 - reverse blocking current vs. output voltage temperature (c) i ds(off) - off switch current (na) 0 1 10 100 1000 10 000 100 000 - 40 - 20 0 20 40 60 80 100 v in = 1 v v in = 2.5 v v in = 1.2 v temperature (c) r ds - on-resistance (m ) 40 45 50 55 60 65 70 75 - 40 - 20 0 20 40 60 80 100 v in = 1.2 v i o = 200 ma 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 i in (na) v out (v) v in = 0.9 v
www.vishay.com 6 document number: 63315 s11-1695-rev. b, 22-aug-11 vishay siliconix sip32452, sip32453 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (internally regulated, 25 c, unless otherwise noted) figure 13 - reverse blocking current vs. temperature figure 15 - turn-on delay time vs. temperature figure 17 - turn-off delay time vs. temperature 0 20 40 60 80 100 - 40 - 20 0 20 40 60 80 100 i in (na) temperature (c) v out = 2.5 v v in = 0.9 v temperature (c) t d(on) - turn-on delay time (s) 0.050 0.055 0.060 0.065 0.070 0.075 0.080 0.085 0.090 0.095 0.100 - 40 - 20 0 20 40 60 80 100 v in = 2.5 v c l = 0.1 f r l = 10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 - 40 - 20 0 20 40 60 80 100 sip32452 v in = 2.5 v c l = 0.1 f r l = 10 t d(off) - turn off delay time (s) temperature (c) figure 14 - en threshold voltage vs. input voltage figure 16 - rise time vs. temperature figure 18 - turn-off delay time vs. temperature v in (v) en threshold voltage (v) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 v ih v il temperature (c) t r - rise switching time (s) 5 6 7 8 9 10 11 12 13 14 - 40 - 20 0 20 40 60 80 100 v in = 2.5 v c l = 0.1 f r l = 10 60 70 80 90 100 110 120 - 40 - 20 0 20 40 60 80 100 t d(off) - turn off delay time (s) temperature (c) sip32453 v in = 2.5 v c l = 0.1 f r l = 10
sip32452, sip32453 vishay siliconix document number: 63315 s11-1695-rev. b, 22-aug-11 www.vishay.com 7 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical waveforms block diagram figure 19 - turn-on time (v in = 1.2 v) figure 21 - sip32452 turn-off time (v in = 1.2 v) figure 23 - sip32453 turn-off time (v in = 1.2 v) figure 20 - turn-on time (v in = 2.5 v) figure 22 - sip32452 turn-off time (v in = 2.5 v) figure 24 - sip32453 turn-off time (v in = 2.5 v) figure 25 - functional block diagram gnd out en in control logic charge pump
www.vishay.com 8 document number: 63315 s11-1695-rev. b, 22-aug-11 vishay siliconix sip32452, sip32453 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 detailed description sip32452 and sip32453 are n-channel power mosfet designed as high side load switch. once enable the device charge pumps the gate of the power mosfet to a constant gate to source volt age for fast turn on time. the mostly constant gate to source voltage keeps the on resistance low through out the input voltage range. when disable, the sip32452 pulls the gate of the output n-channel low right away for a fast turn off delay while there is a build-in turn off delay for the sip32453. the turn off delay for the sip32453 is guaranteed to be at least 30 s. because the body of the output n-channel is always c onnected to gnd, it prevents the current from going back to the input in case the output voltage is higher than the output. application information input capacitor while a bypass capacitor on the input is not required, a 4.7 f or larger capacitor for c in is recommended in almost all applications. the bypass capacitor should be placed as physically close as possible to the input pin to be effective in minimizing transients on the input. ceramic capacitors are recommended over tantalum because of their ability to withstand input current surges from low impedance sources such as batteries in portable devices. output capacitor a 0.1 f capacitor across v out and gnd is recommended to insure proper slew operation. there is inrush current through the output mosfet a nd the magnitude of the inrush current depends on the output capacitor, the bigger the c out the higher the inrush current. there are no esr or capacitor type requirement. enable the en pin is compatible with cmos logic voltage levels. it requires at least 0.1 v or below to fully shut down the device and 1.5 v or above to fully turn on the device. protection against reve rse voltage condition both the sip32452 and sip32453 can block the output current from going to the input in case where the output voltage is higher than the input voltage when the main switch is off. thermal considerations these devices are designed to maintain a constant output load current. due to physical limitations of the layout and assembly of the device the maximum switch current is 1.2 a as stated in the absolute maximum ratings table. however, another limiting characteristic for the safe operating load current is the thermal power dissipation of the package. to obtain the highest power dissipation (and a thermal resistance of 280 c/w) the device should be connected to a heat sink on the printed circuit board. the maximum power dissipation in any application is dependant on the maximum junction temperature, t j(max.) = 125 c, the junction-to-ambient thermal resistance, ? j-a = 280 c/w, and the ambient temperature, t a , which may be formulaically expressed as: it then follows that, assuming an ambient temperature of 70 c, the maximum power dissipation will be limited to about 196 mw. so long as the load current is below the 1.2 a limit, the maximum continuous switch current beco mes a function two things: the package power dissipation and the r ds(on) at the ambient temperature. as an example let us calculate the worst case maximum load current at t a = 70 c. the worst case r ds(on) at 25 c is 65 m ? . the r ds(on ) at 70 c can be extrapolated from this data using the fo llowing formula: r ds(on) (at 70 c) = r ds(on) (at 25 c) x (1 + t c x ? t) where t c is 3900 ppm/c. continuing with the calculation we have r ds(on) (at 70 c) = 65 m ? x (1 + 0.0039 x (70 c - 25 c)) = 76.4 m ? the maximum current limit is then determined by which in case is 1.6 a. under the stated input voltage condition, if the 1.6 a current limit is exceeded the internal die temperature will rise and eventually, possibly damage the device. to avoid possible permanent damage to the device and keep a reasonable design margin, it is recommended to operate the device maximum up to 1.2 a only as listed in the absolute maximum ratings table. 2 8 0 125 (max.) (max.) a a j a j t t t p - = - = - ) ( (max.) (max.) o n ds load r p i <
sip32452, sip32453 vishay siliconix document number: 63315 s11-1695-rev. b, 22-aug-11 www.vishay.com 9 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 package outline micro foot ? : 4 bumps (2 x 2, 0.4 mm pitch, 208 m bump height) notes: 1. laser mark on the backside surface of die. 2. bumps are sac396. 3. 0.050 max. coplanarity. vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?63315 dimension millimeters inches min. nom. max. min. nom. max. a 0.515 0.530 0.545 0.0202 0.0208 0.0214 a1 0.208 0.0081 b 0.250 0.260 0.270 0.0098 0.0102 0.0106 e 0.400 0.0157 d 0.720 0.760 0.800 0.0182 0.0193 0.0203 4 x ? b b u mp n ote 2 a b index-bump a1 w b a 12 1 2 a b mark on backside of die e e d d a a1 n ote 3 recommended land pattern all dimensions in millimeters 0.4 0.4 4 x ? 0.150 to 0.200 solder mask dia. - pad diameter + 0.1
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